1. Field of the Invention
The present invention relates generally to the problem of manufacturing integrated circuits having consistent operating characteristics from one manufacturing batch to the next. More specifically, it relates to the problem of manufacturing precise currents in individual ones of a plurality of bulk fabricated integrated circuits.
2. Description of the Prior Art
Complex electronic circuits may be manufactured in bulk volume at low cost using known integrated circuit fabrication techniques. In these techniques, n-type and p-type conductivity regions are formed one next to the other in a semiconductor substrate such as the substrate 100 shown in FIG. 1. Any alternating arrangement of three or more such regions (PNP or NPN) may be used to create various transistor devices. The P and N regions are typically created by diffusing various impurities (doping agents) through a top surface of the substrate. Top surface dimensions (width and length) of the regions can be controlled to precise tolerances using known photolithographic methods. In cost-effective production techniques it is difficult to keep the depth of the regions within precise tolerances due to process variations (i.e., changes in furnace temperature and impurity concentration levels). This means that transistors from one process batch cannot be guaranteed to be identical to those of another batch.
Within a single batch, wafer, or IC (integrated circuit) chip however, the depth of similar regions will remain generally consistent because integrally formed regions are fabricated under almost identical process conditions. Identical or nearly-identical transistors, resistors, etc. can be formed on individual IC chips. The identical nature of such devices may be exploited to form precision voltage dividers and current splitters. Voltage and/or current magnitudes produced by such precision dividers (or splitters) are precise only in a relative sense. They remain consistently determinable from one manufacturing batch to the next, relative to other voltage or current levels developed internally on the IC chip but not to absolute levels developed outside the chip. Disparities among the absolute output magnitudes of voltages and currents generated by IC's from different fabrication batches create an undesirable situation in which it is difficult to obtain consistent operating characteristics from bulk-produced IC systems.
In FIG. 1, three active devices (transistors) labeled Q.sub.1, Q.sub.2, and Q.sub.3 are shown in sectional perspective with a top layer 110, comprised of metal contacts and insulated gates, exploded away from the top surface of the substrate 100 to reveal a plurality of P and N regions forming the active devices, Q.sub.1, Q.sub.2, and Q.sub.3. The first and second devices, Q.sub.1 and Q.sub.2, comprise a sequence of nearly-identical NPN regions. The third device, Q.sub.3, is fabricated of a dissimilar sequence of PNP regions. Active devices such as NPN bipolar transistors, n-channel FETs (field effect transistors), and the like can be manufactured using the NPN sequences of Q.sub.1 and Q.sub.2. Complementary (dissimilar) active devices such as PNP bipolar transistors, p-channel FET's and the like may be fabricated from the PNP sequence of regions forming Q.sub.3. In FIG. 1, the first and second active devices, Q.sub.1 and Q.sub.2, are shown to be formed as metal-oxide-semiconductor field-effect-transistors (MOSFETs) having respective source, gate and drain terminal portions S.sub.1, G.sub.1, D.sub.1, S.sub.2, G.sub.2, and D.sub.2. The terminal portions are contained within the exploded upper layer 110. It is to be assumed that the dissimilar device, Q.sub.3, has a respective source terminal S.sub.3, gate terminal G.sub.3 and drain terminal D.sub.3 associated with its PNP regions (not shown in FIG. 1).
The n-type regions of the nearly-identical (twin) first and second devices, Q.sub.1 and Q.sub.2, are formed with an identical diffusion depth D.sub.f1. Each of the twin devices has associated therewith a channel length L (distance between source and drain regions) and a channel width W. The width/length dimensions may be formed within precise tolerances as previously mentioned, using known photolithographic techniques. When the respective widths, W.sub.1 and W.sub.2, and the respective lengths, L.sub.1 and L.sub.2, of two twin devices such as Q.sub.1 and Q.sub.2 are identical, the twin devices will be referred to herein as identical twins. Identical twins possess identical electrical characteristics. That is, if identical output voltages, V.sub.DS1 and V.sub.DS2 are developed across the drain and source terminals of two identical-twin devices and equal gate voltages V.sub.GS1, V.sub.GS2 are applied at their gate terminals, then substantially identical currents, I.sub.DS1 and I.sub.DS2 will flow through the output terminals (drain and source terminals) of such devices. This happens because the operating temperatures and fabrication process variables affecting the operating characteristics of two such devices on the same chip are substantially equal. If all factors except the channel widths and channel lengths of two twin devices remain identical, the output currents of the two twin devices will be proportional replicas of one another where the proportionality factor (scaling multipler) is determined by the top view dimensions of the respective devices.
The p-type regions of the third device, Q.sub.3 (PNP) diffuse to a depth D.sub.f3, below the substrate surface, that in general is effectively different from the depth D.sub.f1 of the NPN regions such that it becomes difficult to ascertain any precise relationship between the operating characteristics of Q.sub.3 and those of the twin devices, Q.sub.1 and Q.sub.2. This presents a problem when complementary devices such as the n-channel FET, Q.sub.2 and p-channel FET, Q.sub.3 are to be used in conjunction (e.g., CMOS circuits) to drive an output element that requires precise drive currents.
FIG. 2 is a graph of typical device operating characteristics showing the relationship between an output current I.sub.D of a generic active device Q (FIG. 4) and output and bias voltages, V.sub.D and V.sub.B, across the device. The magnitude of the output current I.sub.D is a function of not only the applied voltages, V.sub.D and V.sub.B, but also of other factors such as the operating temperature, fabrication process variables, and the dimensions of various p-type and n-type regions.
FIG. 3 shows a number of schematic symbols typically used to represent dissimilar active devices. Devices such as an n-channel FET and an NPN bipolar transistor may be formed from regions having an NPN arrangement. Devices such as a p-channel FET and a PNP bipolar transistor may be fabricated at substrate areas having a PNP sequence of regions. Such active devices are represented by the generic circular symbol shown in FIG. 4.
FIG. 4 is a schematic diagram showing one of many possible applications wherein the absolute magnitude of an output current I.sub.D from an active device Q may be of importance. The active device Q is illustrated generically as having a current-controlling gate terminal G, a first output terminal O.sub.1 and a second output terminal O.sub.2. A bias level V.sub.B is applied to the gate terminal G for a time duration t through a switch SW. The output terminals, O.sub.1 and O.sub.2, are placed in series between a voltage source V.sub.cc and a charge accumulating (integrating) capacitor C. When the switch SW is closed for the time duration t, an output current I.sub.D of a specific magnitude is pumped into the integrating capacitor C from the active device Q. An integrated voltage V.sub.C develops across the capacitor C as a result of the total charge stored therein. The voltage change V.sub.C resulting from the charge pumped into the capacitor by the output current I.sub.D is proportional to a product of the absolute value of the output current magnitude I.sub.D and the application time duration t. It may be expressed formally as: EQU .DELTA.V.sub.C =I.sub.D.t/C
where C is the value of the capacitor expressed in farads. The voltage V.sub.C across the charge integrating capacitor C is often used to trigger timing circuits in electronic systems. For applications where the timing must be very precise, it is desirable that the magnitude of the device output current I.sub.D be predictable within precise tolerances. It is difficult however to assure that the output current I.sub.D of each current controlling device Q in every one of a large number of integrated circuit chips (IC's) will be within a desirable set of tolerances. Magnitude determinitive factors such as the operating temperature of each individual IC and fabrication process variables affecting the operating characteristics of each active device on a chip have to be accounted for.